REVIEW PAPER ON NEW TECHNOLOGY BASED NANOSCALE TRANSISTOR

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  Owing to the fact that MOSFETs can be effortlessly assimilated into ICs, they have become the heart of the growing semiconductor industry. The need to procure low power dissipation, high operating speed and small size requires the scaling down of these devices. This fully serves the Moore’s Law. But scaling down comes with its own drawbacks which can be substantiated as the Short Channel Effect. The working of the device deteriorates owing to SCE. In this paper, the problems of device downsizing as well as how the use of SED based devices prove to be a better solution to device downsizing has been presented. As such the study of Short Channel effects as well as the issues associated with a nanoMOSFET is provided. The study of the properties of several Quantum dot materials and how to choose the best material depending on the observation of clear Coulomb blockade is done. Specifically, a study of a graphene single electron transistor is reviewed. Also a theoretical explanation to a model designed to tune the movement of electrons with the help of a quantum wire has been presented.
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  • 1. Advances in Materials Science and Engineering: An International Journal (MSEJ), Vol. 3, No. 1, March 2016 DOI:10.5121/msej.2016.3103 39 REVIEW PAPER ON NEW TECHNOLOGY BASED NANOSCALE TRANSISTOR Banani Talukdar 1 , Dr. P.C.Pradhan 2 and Amit Agarwal3 1 Department of Electronics & Communication Engineering, Sikkim Manipal Institute of Technology, Majitar, East Sikkim. 2 Department of Electronics & Communication Engineering, Sikkim Manipal Institute of Technology, Majitar, East Sikkim. 3 Department of Electronics & Communication Engineering, Sikkim Manipal Institute of Technology, Majitar, East Sikkim. ABSTRACT Owing to the fact that MOSFETs can be effortlessly assimilated into ICs, they have become the heart of the growing semiconductor industry. The need to procure low power dissipation, high operating speed and small size requires the scaling down of these devices. This fully serves the Moore’s Law. But scaling down comes with its own drawbacks which can be substantiated as the Short Channel Effect. The working of the device deteriorates owing to SCE. In this paper, the problems of device downsizing as well as how the use of SED based devices prove to be a better solution to device downsizing has been presented. As such the study of Short Channel effects as well as the issues associated with a nanoMOSFET is provided. The study of the properties of several Quantum dot materials and how to choose the best material depending on the observation of clear Coulomb blockade is done. Specifically, a study of a graphene single electron transistor is reviewed. Also a theoretical explanation to a model designed to tune the movement of electrons with the help of a quantum wire has been presented. KEYWORDS MOSFET, SCE, Moore’s Law, Nanoscale MOSFET, SED, SET, Coulomb Blockade, Graphene, quantum dots, quantum wire. 1. INTRODUCTION The world goes round a transistor. The transistor is the bedrock of the processor. If the transistor was not invented our servers would have been three stories high. Without the transistor, probably the television would still run on vacuum tubes. Had it been the vacuum tubes a lot of tubes, bulbs and heat would have been required to accomplish the fundamental mathematical calculations. Indeed, when moths and other insects turned on the tubes and blowed them out, ‘bug’ was the term coined to represent the scenario. The size of the first transistor was as big as the palm of the hand. But today, forty-two years later a 45 nm Penryn chip has been invented that contains almost about 820 billion transistors [1].The little acclaimed transistor is analogous to an electronic lever. Just as the lever boosts the force required to get a work done, the transistor does the same. It allows for the regulation of a much larger current flowing through a channel by modulating the potency of a smaller current flowing through another channel. The transistors are highly rewarding owing to its small stature, less weight, low heat generation, low power dissipation and faster switching speeds [2]. They also find their utility in a wide range of applications but mainly as switches and amplifiers. One of the utility of a transistor is as an amplifier where a low power signal can be boosted [3]. The voltage of a signal can be surged by an amplifier from a microvolt range to a higher level of milli volt or Volt level. This happens because a small change in the base current results in a large change in the collector current.
  • 2. Advances in Materials Science and Engineering: An International Journal (MSEJ), Vol. 3, No. 1, March 2016 40 When a voltage is enforced unto the base, the transistor turns ON and conducts current over the collector- emitter route. The absence of voltage results in the turning OFF of the transistor. The maximum bias voltage being 0.7 Volt. The switching on and off of the transistor can be done by varying the base current [4]. To curtail the size of the ICs in order to enhance the device functionalities, the transistor has been continuously scaled down. The actual size of the device has been reduced and there has been a rise in the number of transistors within a single IC and has been found to double after every 24 months as stated by Intel’s Co- founder Gordon E. Moore [5]. In the year 1947, the BJT was invented. CMOS which has a compact size and is quite faster in operation came into being in order to supersede the BJT. Subsequent to the invention of the MOSFET in the 1970s, it has been the most prevalent semiconductor device. This paper can be organised in various sections which are as follows. It is started off with the need for miniaturisation, the study of nanoscale MOSFETs and the various problems associated with them. Next a discussion on why Single electron transistor has gained popularity over MOSFETs is presented. A theoretical brief on the Single electron transistor is given followed by the different models of Single electron transistors. A brief explanation regarding the properties of quantum dot materials such as Silicon, Germanium and Silicon Germanium have been provided. This is followed by the study of Graphene Single electron transistor and how it is possible to tune the transport of electrons by means of a quantum wire. Finally, the discussion is wrapped up with a brief conclusion. 2. NEED FOR MINIATURISATION Device miniaturisation or downsizing is essential in order to achieve outstanding device performance at very low costs. It leads to the decrease in the cost per unit function and results in magnified device functioning. Compact dimensions of the circuits decrease the chip area on the whole. Therefore, more and more transistors can be placed in a single chip thereby reducing the manufacturing cost of the chips all together. Another usefulness of device downsizing is the decrease in the device power dissipation which is a boon to the mobile systems as it helps to extend battery life and helps in enhancing the reliability of high- performance systems. Since miniature chips expend lesser power, the energy utilized for each operation is also very less. As a result, the power delay product of the Chips is greatly diminished. On diminishing the MOSFET device dimensions there is a continuous decrease in the intrinsic switching time which is due to the fact that intrinsic delay is approximately equal to the channel length as well as the velocity of the carriers [6]. 3. Nanoscale MOSFETs Metal- oxide- semiconductor field effect transistor (MOSFET) is the substratum of the Integrated Circuit technology, the pillar of present- day computers and telecommunications. MOSFET has been employed tremendously in bulk silicon chips in the form of a dynamic component. The typical CMOS IC designs are executed by employing a pair of N- channel or P- channel MOSFETs. Hence, the penetration as well as its relevance in several fields for our daily needs requires to be barely reminded. Since the invention of the integrated circuit in the 1958 by J.S Kil by, the processing of semiconductor ICs have sustained an exponential growth [7]. This has come into being as a result of the continuous device downsizing or a persistent depletion in the minimum dimensions of the device [8-14]. To work towards attaining data processing as well as memory operations past the sub-micrometer dimensions and to a nanometer scale the decreasing of the size of the silicon MOSFET found integrated circuits have been extensively worked upon. For fabricating, an entire system on a single semiconductor chip it is important to draw attention towards MOSFET channel lengths of the order of 100 nm or below. So far MOSFETs having channel lengths of the order of several tens of nanometer are being produced in bulk whereas sub- 10 nm MOSFET are being illustrated [15].
  • 3. Advances in Materials Science and Engineering: An International Journal (MSEJ), Vol. 3, No. 1, March 2016 A comprehensive research has been going on for acquiring knowledge about the properties of nanostructures like Quantum Dots and two dimensional electron systems. In order to procure requirement for excessive packing density and operating speed with ultra MOSFETs have been repeatedly scaled down. MOSFETs with gate lengths of the order of 10 nm exhibit complete performance. Even MOSFETs as small as 10 nm h Since these structures are acutely small their design, fabrication and understanding requires proper knowledge of device physics at both the sub micrometre and nanometre level. The simplified diagram of cross- section of a nano MOSFET Figure 1: Diagram of a Cross-section of a nano typical dimensions and junction depths Crystal surface in the <100 orientation> is used while constructing N type Silicon wafers [16-21]. A retrograde type of channel doping profile is being utilised that grants for the utilisation of a high subsurface doping (5 × 10 17 the drain electric field from entering the sourc cm-3 is done to retain the threshold voltage at a low level. The electron mobility is increased in the channel. This is done by reducing the impurity scattering in the channel engineering is the term used to depict the adjusting of the channel doping profile channel is interfaced by source/drain extensions having a small junction depth. However, in order to install a contact to the source/drain metal layers, rooted terminals are Arsenic offers high solubility and a small diffusion coefficient, it is used as a dopant. To keep the resistance of the source/drain regions at a subordinate level refractory metal silicide such as Titanium Disilicide, Tantalum Disilicide [32]. The figure below shows a P and N Figure 2: P and N Downsizing the MOSFET results in Short Channel Effects. As a result of the impact of the junction a considerable fragment of the channel region avoids gate control of the subthreshold slope enhances the off state leakage current and this consequently increases the power dissipation. This phenomenon is known as the threshold volt observed that the off state current is enhanced as a result of the slashing of the source junction Advances in Materials Science and Engineering: An International Journal (MSEJ), Vol. 3, No. 1, March 2016 A comprehensive research has been going on for acquiring knowledge about the properties of nanostructures like Quantum Dots and two dimensional electron systems. In order to procure requirement for excessive packing density and operating speed with ultra-low power dissipation; MOSFETs have been repeatedly scaled down. MOSFETs with gate lengths of the order of 10 nm exhibit complete performance. Even MOSFETs as small as 10 nm have been entrenched. Since these structures are acutely small their design, fabrication and understanding requires proper knowledge of device physics at both the sub micrometre and nanometre level. The section of a nano MOSFET is given in the figure below. section of a nano MOSFET having a channel length of 50nm displaying typical dimensions and junction depths [6]. Crystal surface in the <100 orientation> is used while constructing N-channel MOSFETs on P . A retrograde type of channel doping profile is being utilised that grants for the utilisation of a high subsurface doping (5 × 10 17- 3 × 10 18 cm-3). This wards off the drain electric field from entering the source. A small surface doping of the order of 1×1017 3 is done to retain the threshold voltage at a low level. The electron mobility is increased in the channel. This is done by reducing the impurity scattering in the channel [22- used to depict the adjusting of the channel doping profile channel is interfaced by source/drain extensions having a small junction depth. However, in order to install a contact to the source/drain metal layers, rooted terminals are employed Arsenic offers high solubility and a small diffusion coefficient, it is used as a dopant. To keep the resistance of the source/drain regions at a subordinate level refractory metal silicide such as Titanium Disilicide, Tantalum Disilicide, Platinum Silicide, Tungsten Silicide etc., developed The figure below shows a P and N- channel nanoMOSFET. Figure 2: P and N – channel MOSFET [6]. Downsizing the MOSFET results in Short Channel Effects. As a result of the impact of the a considerable fragment of the channel region avoids gate control [33]. The deterioration of the subthreshold slope enhances the off state leakage current and this consequently increases the power dissipation. This phenomenon is known as the threshold voltage roll off. It is also observed that the off state current is enhanced as a result of the slashing of the source junction Advances in Materials Science and Engineering: An International Journal (MSEJ), Vol. 3, No. 1, March 2016 41 A comprehensive research has been going on for acquiring knowledge about the properties of nanostructures like Quantum Dots and two dimensional electron systems. In order to procure the low power dissipation; MOSFETs have been repeatedly scaled down. MOSFETs with gate lengths of the order of 10-100 ave been entrenched. Since these structures are acutely small their design, fabrication and understanding requires proper knowledge of device physics at both the sub micrometre and nanometre level. The is given in the figure below. MOSFET having a channel length of 50nm displaying MOSFETs on P- . A retrograde type of channel doping profile is being utilised that 3). This wards off e. A small surface doping of the order of 1×1017 3 is done to retain the threshold voltage at a low level. The electron mobility is increased in -25]. Channel [26-30]. The channel is interfaced by source/drain extensions having a small junction depth. However, in order employed [31]. As Arsenic offers high solubility and a small diffusion coefficient, it is used as a dopant. To keep the resistance of the source/drain regions at a subordinate level refractory metal silicide such as , Platinum Silicide, Tungsten Silicide etc., developed Downsizing the MOSFET results in Short Channel Effects. As a result of the impact of the . The deterioration of the subthreshold slope enhances the off state leakage current and this consequently increases age roll off. It is also observed that the off state current is enhanced as a result of the slashing of the source junction
  • 4. Advances in Materials Science and Engineering: An International Journal (MSEJ), Vol. 3, No. 1, March 2016 42 barrier to minority carriers via the drain potential; this effect is known as the DIBL [34]. Retrograde or super steep retrograde profiles are utilised, in order to suppress the SCE [35]. In radically small devices a design that has gained recognition for the purpose of alleviating short channel effect is the DG MOSFET [36-38]. Apart from its ability to prevent short channel effect along with the possibility of downsizing to about ~10nm, the DG MOSFET also exhibits great transconductance and an approaching ideal threshold shift. One high- performance nanometer scale MOSFET is the DG MOSFET [39-41]. In order to overcome short channel effects; when a DG MOSFET adjusts itself and consists of a very thin silicon fin the resulting device is known as a FinFET [42,43]. Nano MOSFETs assure high operability, low power consumption and high packing density. The gate-source voltage needed to form a conductive inversion region between the source and the drain is termed as the threshold voltage and for a nano- MOSFET it is about 0.2-0.4 Volts. The transconductance must be maximal and it is given as: gm = ఋூವೄ ఋ௏ವೄ . (1.1) The channel conductance of a nano-MOSFET is defined as: gDS= ఋூವೄ ఋ௏ವೄ (1.2) under constant VGS. gDS should be maximum for operation in the linear area and for operation in the saturation area it must be minimum. NanoMOSFET exhibits a characteristic termedas subthreshold swing which demarcates the variation in the gate-source voltage essential to reduce the drain- source current by one decade. This subthreshold swing is given by S = ln 10 ఋ௏ಸೄ ఋ௟௡ூವೄ (1.3) As soon as IDS drops to 1/10th the worth of threshold voltage. In a nano MOSFET the S parameter inflicts a breaking point on the threshold voltage since the current has to be small enough to handle the off-state current. 4. PROBLEMS ASSOCIATED WITHNanoMOSFETs: Few issues come up in the nano MOSFETs and they have been explained sequentially as to where they originate. The problems can be explained as below: 4.1 Channel The problems that arise in the channel are categorised below and can be explained as given below: 4.1.1 Sub threshold leakage current When VGS < Vth, a diffusion current flows between the drain and the source terminal. This diffusion current dictates the subthreshold leakage current. This subthreshold leakage current is also the weak inversion conduction current. As a switching device, it is contemplated to be a non- ideal characteristic of MOSFETs. The weak inversion conduction current can be represented as below [44]: Isubth = µCdep ( ௐ ௅ ) VT 2 (exp ( (୚ృ౏ି୚౪౞) ఎ௏೅ )(‫ܫ‬ − exp ି௏ವೄ ௏೅ )) (1.4)
  • 5. Advances in Materials Science and Engineering: An International Journal (MSEJ), Vol. 3, No. 1, March 2016 43 Where Cdep= ට ఌೄ೔௤ேೞೠ್ ସఝಶ indicates the capacitance of the depletion region beneath the gate area, VT represents the thermal voltage and is given by ௞் ௤ and lastly n denotes the sub threshold parameter which can be given as 1+Cdep/Cox.The subthreshold slope can be generated from the above equation. With an increasing VGS and decreasing Vth, Isubthincreases exponentially. Calculating the partial derivative of log10 Isubthwith respect to VGSresults in a constant slope labelled sub-threshold slope and this is given as: SS= ఋ௟௢௚భబூೞೠ್೟೓ ఋ௏ಸೄ = ூ ୪୬ ଵ଴ ூೞೠ್೟೓ . ఋூೞೠ್೟೓ ఋ௏ಸೄ (1.5) It can be concluded here that with decreasing voltage, the transistor turns off unanticipated. For the transistor to turn off adequately, S must be designed such that it is as small as possible. At room temperature, S is always greater than 2.3VT (~ 60mV/dec). This indicates how strongly the gate contact can command the channel surface potential. Utilising a thinner gate oxide thickness S can be made petite. This leads to a larger Cox. Lowering the substrate doping concentration also results in a smaller S. 4.1.2 Threshold Voltage variation The device speed and sub threshold leakage current is analogous to the threshold voltage (Vth) change. As a result, it needs to be curtailed. Chiefly, this can be justified in terms of two parameters. One is Vth roll off and the other is DIBL (drain induced barrier lowering). In an identical synonymous wafer, the transistors with a dissimilar channel length (L) results in a varied Vth. Owing to a condensed channel length, the threshold voltage dwindles thus exhibiting Vth roll off. In addition to reducing Vth as a result of growing drain voltage describes DIBL. Vth roll off and DIBL springs up from the descending potential barrier between the drain and the source. This happens because of the rise in the charge – sharing effects amidst the channel and the source/drain depletion regions. Charge – sharing effects causes a transistor to utilize less gate voltage in order to deplete the substrate that lies below the gate dielectric and reduces Vth [44 - 46]. Alongside an added rise in the drain voltage the depletion region about the drain goes on to lengthen to the source depletion region and eventually fuse together ahead of junction breakdown. On the other hand, the drain current escalates as a result of the subsistence of a parasitic current route. This is known as punch- through. A rise in the comprehensive substrate doping will help in prohibiting punch through. Yet a greater doping will also lead to an upsurge in the sub threshold swing. Hence decreasing the leakage current is not feasible [47, 45, 48]. These entire phenomena are accredited as Short Channel Effects. SCEs influence the rise in power consumption and hence to alleviate SCEs nano MOSFETs came into bein
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